A 12-bit 10-MS/s Calibration-Free Successive-Approximation Analog-to-Digital Converter
碩士 === 國立成功大學 === 電機工程學系 === 107 === A 12-bit 10-MS/s calibration-free successive-approximation register (SAR) analog-to-digital converter (ADC) in 180-nm process is presented in this thesis. This work adopts two techniques, namely residue oversampling and detect-and-skip (DAS) algorithm. For each s...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2019
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| Online Access: | http://ndltd.ncl.edu.tw/handle/22jsa9 |