| Summary: | 博士 === 國立交通大學 === 電子研究所 === 107 === With the continuous evolution of communication technology and integrated circuit (IC), wireless and wireline communication devices had become essential in daily life. All microelectronic products must meet the reliability specifications to be safely used and provide moderate life time. Electrostatic discharge (ESD) protection ability has become one of the important concerns on the reliability of IC products. Most of the failures and damages found in ICs were demonstrated to be related to ESD events. On-chip ESD protection circuits must be added for all I/O pads in IC products to sustain the HBM 2 kV and CDM 500 V for the reliability specifications. However, applying ESD protection devices at the I/O pads inevitably introduce some negative impacts to the high-speed circuit performance due to their parasitic effects. The parasitic capacitance caused by ESD protection devices will strongly degrade the bandwidth in normal high-frequency operation. Thus, the parasitic effects of the ESD protection devices should be minimized. Besides, to sustain good ESD robustness, the active power-rail ESD clamp circuit plays an important role in whole-chip ESD protection design. Unfortunately, the traditional RC-based power-rail ESD clamp with NMOS of large size often suffered a mis-triggering issue in hot plug-in condition. The power-rail ESD clamp circuit should be designed to sustain good ESD robustness without influencing the circuit performance.
In Chapter 2, a new SCR-based ESD protection device is used to meliorate the ESD protection effectiveness and parasitic capacitance for high-speed I/O applications. By using a P+ and N+ junction contact with silicide to shorten the path of the SCR, the trigger voltage and turn-on resistance can be reduced to get good ESD robustness.
In Chapter 3, a new distributed ESD protection structure with the stacked diodes with embedded SCR (SDSCR) is proposed to improve the bandwidth and input resistance of ESD protection circuit for broadband RF applications. The ESD protection devices of the proposed circuit are put under the I/O pad to reduce layout area and can discharge the ESD current immediately. From the experimental results, the proposed distributed ESD protection circuit with the SDSCRs can effectively sustain the HMM stress of 5 kV without influencing RF performance.
In Chapter 4, a new power-rail ESD clamp circuit with both timing and voltage-level detection is proposed against false trigger events. The experimental results in a 0.18-μm 1.8-V CMOS process have successfully verified that the proposed power-rail ESD clamp circuit can sustain good ESD robustness (HBM 5.2 kV) without suffering the false trigger issue (high immunity for transient waveform with 10 ns rise time). The standby leakage current along the proposed power-rail ESD clamp circuit under the normal circuit operating condition has been also effectively reduced (270 nA) by adding a feedback NMOS in series into the diode string.
In Chapter 5, a new diode-triggered quad-silicon-controlled rectifier (DTQSCR) is proposed and realized in a 0.18-μm 1.8-V/3.3-V CMOS process to effectively protect the interface circuit between separated power domains. Comparing to the traditional ESD protection design with GGNMOS, and the FOM (ESD level / layout area) of the proposed design is significantly improved ~36% to protect the interface circuits across separated power domains.
In Chapter 6, a simple structure for power-rail ESD clamp circuit with both timing and voltage-level detection is proposed against false trigger events. A RC stage is used for dv/dt detection and a diode string is used to detect the over-stress voltage level during ESD events. The experimental results in a 0.18-μm 1.8-V CMOS process have successfully verified that the proposed power-rail ESD clamp circuit can sustain good ESD robustness (HBM 4.8 kV) without suffering the false trigger issue (high immunity for transient waveform with 10 ns rise time). By using fully isolated polysilicon diodes, the standby leakage current of the proposed power-rail ESD clamp can be effectively reduced (below 1 μA).
Chapter 7 summarizes the results of this dissertation, where the future works based on the new proposed designs and test structures are discussed as well. The related works in this dissertation have been published in several international journals or conferences.
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