Low-Capacitance and High-Reliable ESD Protection Designs in CMOS Technology
博士 === 國立交通大學 === 電子研究所 === 107 === With the continuous evolution of communication technology and integrated circuit (IC), wireless and wireline communication devices had become essential in daily life. All microelectronic products must meet the reliability specifications to be safely used and provi...
Main Authors: | Chen, Jie-Ting, 陳界廷 |
---|---|
Other Authors: | Ker, Ming-Dou |
Format: | Others |
Language: | en_US |
Published: |
2018
|
Online Access: | http://ndltd.ncl.edu.tw/handle/6m2xcc |
Similar Items
-
DESIGN AND IMPLEMENTATION OF ESD PROTECTION CIRCUITS IN NANOSCALE FULLY SILICIDED CMOS TECHNOLOGY
by: Yeh, Chih-Ting, et al.
Published: (2013) -
ESD Protection Design with Ultra-Low Parasitic Capacitance
by: Huang, Guo-Lun, et al. -
High-Voltage-Tolerant ESD Protection Design in Low-Voltage CMOS Processes
by: Wei-Jen Chang, et al.
Published: (2007) -
High-Reliability and Low-Capacitance Bond Pad Design for CMOS Integrated Circuits
by: Peng, Jeng-Jie, et al.
Published: (2002) -
Advanced ESD Protection Design for Nanoscale CMOS Processes
by: Federico Agustin Altolaguirre, et al.
Published: (2016)