Simulation and Analysis of III-V and Si Negative-Capacitance FETs Considering Quantum Capacitance

碩士 === 國立交通大學 === 電子研究所 === 107 ===  This thesis investigates the subthreshold characteristics and ON-state inversion charges (QINV) for gate-all-around (GAA) and double-gate (DG) III-V/Si negative-capacitance FETs (NCFETs) considering quantum capacitance (Cq) by using numerical simulation coupled w...

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Bibliographic Details
Main Authors: Lin, Shih-Han, 林詩涵
Other Authors: Su, Pin
Format: Others
Language:en_US
Published: 2018
Online Access:http://ndltd.ncl.edu.tw/handle/j797vp
Description
Summary:碩士 === 國立交通大學 === 電子研究所 === 107 ===  This thesis investigates the subthreshold characteristics and ON-state inversion charges (QINV) for gate-all-around (GAA) and double-gate (DG) III-V/Si negative-capacitance FETs (NCFETs) considering quantum capacitance (Cq) by using numerical simulation coupled with 1D static Landau-Khalatnikov equation. Our study indicates that, albeit the Cq is beneficial to the subthreshold characteristics of NCFETs, its impacts on the ON-state QINV boosting depend on the device structure. Compared with the Si counterpart, the III-V GAA NCFET get smaller negative-capacitance induced QINV boost because of the non-monotonic intrinsic inversion capacitance (CINV) characteristic due to its 1D density-of-states (DOS). With appropriate remnant polarization (Pr) value, the III-V DG NCFET can get larger QINV boost than the Si counterpart because the III-V channel exhibits the step-like CINV due to its 2D DOS.