Investigation on Vertically Stacked Gate-All-Around Nanosheet Poly-Si Junctionless CMOS Transistors
碩士 === 國立交通大學 === 電子物理系所 === 107 === The GAA Nanosheet Poly-Si JL FETs have been successfully fabricated by only two simple steps that the dry etching process follows by wet etching. The dimension of gate stack of WM = 40 nm with Hp,1 × Wp,1 of top layer poly-Si is 8 nm × 30 nm, and Weff is 76 nm. T...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2018
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| Online Access: | http://ndltd.ncl.edu.tw/handle/459ufp |