Effective Construction of Routing Trees for 2D Mesh On-Chip Networks with Over-Size IP Cores
碩士 === 國立東華大學 === 資訊工程學系 === 107 === With the rapid development of semiconductor technology, it has become feasible to integrate tens or even hundreds of intellectual properties (IP) cores on a single chip. Such highly integrated system-on-chip (SoC) can implement very complex functions on a single...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2018
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/t8exh5 |