An Area-Efficient 12-bit 20 MHz Two-Step SAR ADC
碩士 === 國立清華大學 === 電子工程研究所 === 107 === This thesis describes an analog-to-digital converter (ADC) for FHD image sensors. The ADC specification is 12-bit resolution and the sampling rate is 20 MHz. The architecture of this ADC is two-step successive approximation register (SAR) ADC. The disadvantage o...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2019
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| Online Access: | http://ndltd.ncl.edu.tw/handle/t295d5 |