An Area-Efficient 12-bit 20 MHz Two-Step SAR ADC

• Main Authors: Chen, Chien-Chung, 陳建仲
• Other Authors: Hsu, Yung-Jane Klaus
• Format: Others
• Language: zh-TW
• Published: 2019
• Online Access: http://ndltd.ncl.edu.tw/handle/t295d5

碩士 === 國立清華大學 === 電子工程研究所 === 107 === This thesis describes an analog-to-digital converter (ADC) for FHD image sensors. The ADC specification is 12-bit resolution and the sampling rate is 20 MHz. The architecture of this ADC is two-step successive approximation register (SAR) ADC. The disadvantage of the traditional SAR ADC is the great area of capacitor. When we add every 1-bit resolution, the area of the capacitor will double. In this thesis, the number of unit capacitor of the two-step SAR ADC is reduced to 1/16th of that of a conventional 12-b SAR ADC. The prototype was fabricated using TSMC 0.18um 1P6M CMOS technology. At a 1.8-V supply and 20-M Hz sampling rate, simulations showed that the ADC achieves a SNDR of 71.78dB, an ENOB of 11.63 and power consumes 3.62mW. The chip area including I/O pad is 1.109mm2 .The simulating results of static analysis DNL and INL are （1.004 / -1 LSB） and （0.756 / -1.007 LSB）. Measurements showed that the chip layout might not be symmetric enough and it might degrade the ADC performance.