| Summary: | 博士 === 國立清華大學 === 電子工程研究所 === 107 === This work focuses on the wideband measurement technique development of the conducted electromagnetic compatibility (EMC) for IC, and presents the chip level design strategies. For the electromagnetic interference (EMI) test, a 1-Ω probe is presented to comply with the IEC61967-4 standard. The insertion loss specification of 34±2 dB is achieved within 1 GHz bandwidth. To meet the demand of high speed/high frequency testing, the on-chip test setup is proposed. By implementing the 1-Ω current probe and 150-Ω voltage probe in the integrated passive device (IPD) technology, the bandwidth could reach up to 15 GHz. With the flip-chip technology, the chip level EMI test is performed. Furthermore, an active 1-Ω probe is proposed to overcome the high loss property of the conventional passive probe. By integrating the precise 1-Ω resistor design and a wide band amplifier, the insertion loss is reduced form 34 dB to 18 dB with the operating bandwidth of 3 GHz. A MCU chip is tested to demonstrate that the active probe shows a better ability of detecting interference than the conventional passive probe. For the electromagnetic susceptibility (EMS) test, the bandwidth of the IEC62132-4 standard, the direct power injection (DPI) method, is extended from 1 GHz to 18 GHz. A linear low dropout regulator (LDO) IC is tested to demonstrate that the IC would still malfunction when it encounters with the interference at the frequency higher than its operating frequency. Finally, two chip level EMC solutions are proposed. The slew rate controller could change the rising/falling rate of a signal. It reduces the high frequency contents of the signal and results in the improved EMI issue. Besides, a decoupling capacitor (decap) which stacks MOM and MOS capacitors is proposed. It provides extra 17% capacitance compared with the MOS capacitor. By embedding the proposed decaps into a LDO, the immunity can be improved with a maximum value of 11.6 dB.
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