Applying Hybrid Design of Experiments and Assembly Approaches in IC Packaging Process

• Main Authors: Chia-Hao Hu, 胡家豪
• Other Authors: 湯譯增
• Format: Others
• Language: zh-TW
• Published: 2019
• Online Access: http://ndltd.ncl.edu.tw/handle/9mmk5p

碩士 === 國立臺南大學 === 綠色能源學科技學系碩士在職專班 === 107 === Semiconductor and wafer assembly & testing process is one specialized division of high-tech-industry, and that is necessary to proceed high-precision wafer manufacturing under strict terms of cooperation with multi-process chain. The intense competition between wafer nanometer pitch technology and flexible circuit board (COF) bonding are much more difficult for assembly and wafer probing factories to ensure perfect yield quality and high efficiency. Currently, the trend of semiconductor back-end technology is not only to improve the IC assembly and circuit testing process yield, but also to provide a differentiated high-precision and low-deviation control service to meet the "One Stop Shopping; Turn-key " requirements of the integrated circuit design house. Furthermore, to create a mutually beneficial business model for all the semiconductor procedure. The purpose of this research is to explore how the integrated circuit and substrate bonding procedure can maximize the benefits and optimize the entire quality of semiconductor chain. All in all, the results of the study is to control the key factors by optimization parameters decision, including:（1）Efficiency of operation up to 49.2% and cost reduction for 50%; (2) the mechanism analysis of the inner lead bonding technology; (3) The monitor method by automatic inspection and feedback mechanism for high-precision fine pitch products. To improve the assembly technology and strategy, the wafer bonding and testing unit must strictly control its development roadmap. To optimize the back-end technology and enhance the production capacity will be the target. Keywords: Semiconductor assembly, Gold bump, Inner lead bonding