The back-end of layout vs. schematic checker for passive multilayer microwave circuit and three-dimensional multiuser display environment
碩士 === 國立臺灣大學 === 電子工程學研究所 === 107 === An optimized algorithm of layout versus schematic checker is presented in this thesis. The checker is divided into two parts. First, the component extraction from layout would be exported to net-list. Second, we would compare the discrepancy of the net-lists be...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2019
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| Online Access: | http://ndltd.ncl.edu.tw/handle/duxajw |