Design of a Sub-Sampling Phase-Locked Loop with a Robust-Locking Frequency-Locked Loop
碩士 === 國立臺灣大學 === 電子工程學研究所 === 107 === Sub-sampling technique has been adopted in the PLL to reduce in-band phase noise nowadays. Hence, the loop bandwidth can be expanded to reduce the RMS jitter furthermore. However, the sub-sampling loop (SSL) can not detect large frequency. It needs an additiona...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2019
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| Online Access: | http://ndltd.ncl.edu.tw/handle/t5tdy5 |