A 10-bit 200-MS/s SAR ADC with Dual-loop Asynchronous Control in 90nm CMOS
碩士 === 國立臺灣大學 === 電子工程學研究所 === 107 === This thesis proposes a control architecture for successive-approximation (SAR) analog-to-digital converters (ADCs). A single-channel 10-bit 200-MS/s asynchronous SAR ADC in 90-nm CMOS process was realized based on the proposed architecture. The proposed archite...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2019
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| Online Access: | http://ndltd.ncl.edu.tw/handle/69y5f4 |