A 10-bit 200-MS/s SAR ADC with Dual-loop Asynchronous Control in 90nm CMOS

• Main Authors: Li-Yuan Hsu, 許力元
• Other Authors: 陳中平
• Format: Others
• Language: en_US
• Published: 2019
• Online Access: http://ndltd.ncl.edu.tw/handle/69y5f4

碩士 === 國立臺灣大學 === 電子工程學研究所 === 107 === This thesis proposes a control architecture for successive-approximation (SAR) analog-to-digital converters (ADCs). A single-channel 10-bit 200-MS/s asynchronous SAR ADC in 90-nm CMOS process was realized based on the proposed architecture. The proposed architecture is a dual-loop asynchronous control scheme. It reduce the waste time problem in LSB steps, which result from the architectural limitation of a conventional asynchronous control. Therefore, increase the speed. The physical design was implement in TSMC 90-nm CMOS process. The core area is 115 µm × 192 µm. From post-layout simulation, at 0.9 V supply voltage and 200-MS/s sampling rate, the total power consumption is 1.61 mW, and ENOB is 9.26 bits. The prediction of maximum 1-sigma DNL and INL are 0.298 LSB and 0.35 LSB respectively This design is in fabrication process and was taped out at 2019/07/10。The chip out was scheduled to 2019/09/26.