A 10-bit 200-MS/s SAR ADC with Dual-loop Asynchronous Control in 90nm CMOS

A 10-bit 200-MS/s SAR ADC with Dual-loop Asynchronous Control in 90nm CMOS

碩士 === 國立臺灣大學 === 電子工程學研究所 === 107 === This thesis proposes a control architecture for successive-approximation (SAR) analog-to-digital converters (ADCs). A single-channel 10-bit 200-MS/s asynchronous SAR ADC in 90-nm CMOS process was realized based on the proposed architecture. The proposed archite...

Full description

Bibliographic Details
Main Authors:	Li-Yuan Hsu, 許力元
Other Authors:	陳中平
Format:	Others
Language:	en_US
Published:	2019
Online Access:	http://ndltd.ncl.edu.tw/handle/69y5f4

Similar Items

A 10-MS/s SAR-ASSISTED TWO-STAGE PIPELINE ADC IN 90 nm CMOS
by: Shu-wen Hsu, et al.
Published: (2019)

A 6.94-fJ/Conversion-Step 12-bit 100-MS/s Asynchronous SAR ADC Exploiting Split-CDAC in 65-nm CMOS
by: Manxin Li, et al.
Published: (2021-01-01)

12Bit 200Ms/s Pipeline ADC
by: Liao, Yu-Cheng, et al.
Published: (2018)

Implementation of a 14-bit 200-MS/s Current-Steering DAC with Digital Foreground Calibration in 90-nm CMOS
by: Ho, Zong-Yue, et al.
Published: (2014)

A 13-bit 3-MS/s Asynchronous SAR ADC with a Passive Resistor Based Loop Delay Circuit
by: Hyungyu Ju, et al.
Published: (2019-02-01)

A 6-bit 1-GS/s 30-mW ADC in 90-nm CMOS Technology
by: Yuan-Ching Lien, et al.
Published: (2007)

A 12-bit 25MS/s Asynchronous SAR ADC With All Digital Background Calibration
by: Lei, Kin-Man, et al.
Published: (2012)

A 0.5V 12-bit SAR ADC using adaptive time-domain comparator with noise optimization in 90 nm CMOS
by: Kao, Chen-Che, et al.
Published: (2017)

A 2 GSps, 8-Bit Folding and Interpolation ADC with Foreground Calibration in 90 nm CMOS Technology
by: Yi Zhang, et al.
Published: (2017-01-01)

Design of an 8-bit Successive Approximation Pipelined Analog to Digital Converter (SAP-ADC) in 90 nm CMOS
by: Kotti, Vivek
Published: (2017)

An 8-bit 1.1-Msamples/s SAR ADC for CMOS image sensor
by: Li-Hao Liu, et al.
Published: (2007)

A 1 GS/s 12-Bit Pipelined/SAR Hybrid ADC in 40 nm CMOS Technology
by: Jianwen Li, et al.
Published: (2020-02-01)

Implementation of a Digitally Calibrated 12-bit 25MS/s SAR ADC with an Asynchronous Clock Generator
by: Tsau, Wen-Shang, et al.
Published: (2013)

A Design of Low-Power 10-bit 1-MS/s Asynchronous SAR ADC for DSRC Application
by: Deeksha Verma, et al.
Published: (2020-07-01)

A low power 10bit 200Ms/s Pipelined ADC
by: Chen, Yi-Ting, et al.
Published: (2017)

A study of SAR ADC and implementation of 10-bit asynchronous design
by: Kardonik, Olga
Published: (2013)

A 2.6 GS/s 8-Bit Time-Interleaved SAR ADC in 55 nm CMOS Technology
by: Dong Wang, et al.
Published: (2019-03-01)

Current-Mode SAR-ADC In 180nm CMOS Technology
by: Eilertsen, Bård Egil
Published: (2012)

A 12bit 200MS/s Time-interleaved Hybrid-SAR ADC with Two-bit-per-cycle and Digital-slope Conversions
by: Lih, Yu-Hsin, et al.
Published: (2018)

A 10-Bit 50-MS/s SAR ADC for Dual-Voltage Domain Portable Systems
by: Wei-HaoTsai, et al.
Published: (2015)

A 12-Bit 200 MS/s Pipelined-SAR ADC Using Back-Ground Calibration for Inter-Stage Gain
by: Junjie Wu, et al.
Published: (2020-03-01)

Radiation tolerant low power 12 bit ADC in 130 nm CMOS technology
by: Sousa, Filipe José Pereira Alves de
Published: (2009)

A 12-bits 50MS/s Pipelined-SAR ADC in 0.18μm CMOS Technology
by: Wei-Jin Lu, et al.
Published: (2014)

A 10-bit 110-MS/s SAR ADC with 2.5-bit Predictive Capacitor Switching Procedure
by: Nan-YuanWang, et al.
Published: (2011)

A 10-bit 200-MS/s Pipelined ADC with Mixed-Mode Sampling Technique
by: Yi-Xian Chen, et al.
Published: (2009)

A 10-BIT 200MS PIPELINED ADC FOR HIGH DEFINATION VIDEO DECODER
by: Chia-ching Lin, et al.
Published: (2010)

A Low-Power 12-Bit 20 MS/s Asynchronously Controlled SAR ADC for WAVE ITS Sensor Based Applications
by: Khuram Shehzad, et al.
Published: (2021-03-01)

An Energy-efficient 32-bit multiplier architecture in 90nm CMOS
by: Mehmood, Nasir
Published: (2006)

DESIGN OF ULTRA HIGH SPEED FLASH ADC, LOW POWER FOLDING AND INTERPOLATING ADC IN CMOS 90nm TECHNOLOGY
by: Hiremath, Vinayashree
Published: (2010)

A 10-bit 27-MS/s Low Power SAR ADC
by: Meng-FaYang, et al.
Published: (2010)

Design and Implementation of a 12-bit 100-MS/s SAR ADC
by: Chia-Wei - Yen, et al.
Published: (2016)

Design and Implementation of a 10-bit 160-MS/s SAR ADC
by: Hsuan-Chin Yeh, et al.
Published: (2016)

Area-efficient readout with 14-bit SAR-ADC for CMOS image sensors
by: Aziza Sassi Ben, et al.
Published: (2016-01-01)

A Study of Successive Approximation Registers and Implementation of an Ultra-Low Power 10-bit SAR ADC in 65nm CMOS Technology
by: Hedayati, Raheleh
Published: (2011)

Modeling and Design of a Dual-Residue Pipelined ADC in 130nm CMOS
by: Steen-Hansen, Eirik
Published: (2012)

16-bit Digital Adder Design in 250nm and 64-bit Digital Comparator Design in 90nm CMOS Technologies
by: Boppana, Naga Venkata Vijaya Krishna
Published: (2014)

An 8-bit 100MS/s CMOS Pipelined ADC With Improved Loading-Free Architecture
by: 夏竹緯
Published: (2008)

A 10-bit 100-MS/s Power-Efficient Flash SAR ADC
by: Chao-FangTsai, et al.
Published: (2011)

A New CMOS Temperature Sensor with 10-Bit SAR ADC for RFID Applications
by: Chien-Nan Chen, et al.
Published: (2011)

A 10-bit 250MS/s pipelined ADC
by: Jian-Feng Shiu, et al.
Published: (2007)