The Design and Implementation of the Frequency-Drift-Compensated Phase-Locked Loop
博士 === 國立臺灣大學 === 電子工程學研究所 === 107 === This dissertation consists of two parts. The first part aims to design a frequency-drift-compensated (FDC) phase-locked loop (PLL). The second part implements a 10 bit analog-to-digital converter (ADC) which uses to increase the resolution of the frequency-drif...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2019
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| Online Access: | http://ndltd.ncl.edu.tw/handle/jj9jr8 |