The Design and Verification of an IP Core for Pipeline AES Based on AXI4 Interface
碩士 === 國立臺灣科技大學 === 電子工程系 === 107 === In this thesis, a pipelined architecture of AES Encryption/Decryption based on AXI4 interface is proposed. This architecture emphasizes area and throughput, reduces hardware cost and improves its computing performance. According to the AES algorithm, the input d...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2019
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| Online Access: | http://ndltd.ncl.edu.tw/handle/t2z5np |