| Summary: | 碩士 === 國立臺灣科技大學 === 電子工程系 === 107 === Since NAND flash memory has limited P/E cycles, it could be unusable after exceeding the limited P/E cycles, and the main reason is the wear-out phenomenon in the flash memory cell. Under the influence of this phenomenon, any data can only be safely stored in the flash memory for a limited time (i.e., the retention time). As the retention time increases, the retention error rate continues to rise, and the final retention error rate could exceed the ECC capability. Since the retention error is the main error of the flash memory and its error rate is dependent on different states, some mitigation methods for retention errors are proposed. In the thesis, we propose a retention error mitigation method based on TLC NAND flash memory. The proposed method contains a write position selection scheme (including a new flag design and state coding optimization) and a word-line block classification mechanism for the wear-leveling issue. According to the experimental results, we can reduce the retention error rate and increase the lifetime of TLC NAND flash memory.
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