Via Ladder-aware Detailed Placement
碩士 === 國立臺灣科技大學 === 電機工程系 === 107 === With the feature size shrinking down to 7 nm and beyond, the impact of wire resistance is significantly growing, and the circuit delay incurred by the metal wires is noticeable raising. To address this issue, a new technique called via ladder (or via pillar) ins...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2019
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| Online Access: | http://ndltd.ncl.edu.tw/handle/29x6f4 |