A Study of Layout Design on ESD Robustness in 300V UHV nLDMOS Devices
碩士 === 國立聯合大學 === 電子工程學系碩士班 === 107 === As the semiconductor technology is gradually developing and the dimensions of integrated circuits are also same time shrunk. Therefore, the functional diversity, speed and price are superior to those of the past. However the interference by external noise on c...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2019
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| Online Access: | http://ndltd.ncl.edu.tw/handle/98367w |