Chip Design of Redundant Compensation Capacitor SAR ADC with Building-in-self-testing
碩士 === 國立臺北科技大學 === 電子工程系 === 107 === In this thesis, the chip design of a redundant compensation capacitor SAR ADC with building-in-self-testing is proposed. The BIST function is integrated into the chip. The output waveform from the testing source can be used to test the accuracy of the ADC. A new...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2019
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/9rgvf7 |