Modeling of SET-State Retention Failure Time and Its Voltage Accelerating Qualification Method in a Post-Cycling Resistive Switching Memory
碩士 === 國立交通大學 === 電子研究所 === 108 === In this thesis, we observe that the SET-state [i.e., low-resistance state (LRS)] current degradation exhibits a two-stage evolution in a hafnium oxide resistive switching memory. The decline of current follows an inverse power law time-dependence (I∝t-n) in the se...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2019
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| Online Access: | http://ndltd.ncl.edu.tw/handle/xbjtpt |