VLSI support for scheduling and buffer management in high speed packet-switched networks
This thesis presents a number of new approaches for designing fast, scalable queuing structures in VLSI for very high speed packet-switched networks. Such queuing structures are necessary for implementing packet buffers in switches and routers that have multi Gigabit-per-second (Gb/s) ports. The...
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| Format: | Others |
| Language: | English |
| Published: |
2009
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| Online Access: | http://hdl.handle.net/2429/10812 |