Optimizing network-on-chips for FPGAs
As larger System-on-Chip (SoC) designs are attempted on Field Programmable Gate Arrays (FPGAs), the need for a low cost and high performance Network-on-Chip (NoC) grows. Virtual Channel (VC) routers provide desirable traits for an NoC such as higher throughput and deadlock prevention but at signific...
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| Language: | English |
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University of British Columbia
2013
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| Online Access: | http://hdl.handle.net/2429/44343 |