Low power techniques for global communication in CMOS VLSI
Technology trends and especially portable applications are adding a third dimension (power) to the previously two-dimensional (speed, area) VLSI design space. A large portion of power dissipation in high performance CMOS VLSI is due to the inherent difficulties in global communication at high rates...
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| Language: | ENG |
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ScholarWorks@UMass Amherst
1996
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| Online Access: | https://scholarworks.umass.edu/dissertations/AAI9709658 |