Layout and logic techniques for yield and reliability enhancement
Several yield and reliability enhancement techniques have been proposed for the compaction, routing and technology mapping stages of VLSI design. For yield, we modify the existing layouts to reduce the sensitivity of the design to random point defects, which are the main yield detractors in today�...
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| Language: | ENG |
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ScholarWorks@UMass Amherst
1998
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| Online Access: | https://scholarworks.umass.edu/dissertations/AAI9841852 |