Static scheduling of multi domain circuits for functional verification
With the advent of System-On-a-Chip (SOC) design, many Application Specific Integrated Circuits (ASICs) now require multiple design clocks that operate asynchronously to each other. This design characteristic presents a significant challenge when these ASIC designs are mapped to hardware based verif...
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| Language: | ENG |
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ScholarWorks@UMass Amherst
2005
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| Online Access: | https://scholarworks.umass.edu/dissertations/AAI3179893 |