Fast floorplan generation for dataflow designs
Increasing complexity of ICs and system on chip (SOC) requires the development of advanced CAD tools that will raise the level of design abstraction from register transfer level (RTL) to algorithmic and behavioral levels. One of the tools needed for the designer is to do fast design space exploratio...
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| Language: | ENG |
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ScholarWorks@UMass Amherst
2006
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| Online Access: | https://scholarworks.umass.edu/dissertations/AAI3242300 |