On detection, analysis and characterization of transient and parametric failures in nano-scale CMOS VLSI
As we move deep into nanometer regime of CMOS VLSI (45nm node and below), the device noise margin gets sharply eroded because of continuous lowering of device threshold voltage together with ever increasing rate of signal transitions driven by the consistent demand for higher performance. Sharp eros...
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| Language: | ENG |
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ScholarWorks@UMass Amherst
2010
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| Online Access: | https://scholarworks.umass.edu/dissertations/AAI3409842 |