Equivalence checking of arithmetic expressions with applications in DSP synthesis
Numerous formal verification systems have been proposed and developed for FSM based control units (notably SMV (71) as well as others). However, most research on the equivalence checking of datapaths is still confined to the bit- or word-level. Formal verification of arithmetic expressions and synth...
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| Language: | ENG |
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ScholarWorks@UMass Amherst
1996
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| Online Access: | https://scholarworks.umass.edu/dissertations/AAI9619461 |