Characterization, Clock Tree Synthesis and Power Grid Dimensioning in SiLago Framework
A hardware design methodology or platform is complete if it has the capabilities to successfully implement clock tree, predict the power consumption for cases like best and worst Parasitic Interconnect Corners (RC Corners), supply power to every standard cell, etc.This thesis has tried to solve the...
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| Format: | Others |
| Language: | English |
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KTH, Skolan för elektroteknik och datavetenskap (EECS)
2019
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| Online Access: | http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-247794 |