Global clock distribution in the SiLago platform
The extreme evolution of Very Large Scale Integration (VLSI) design has followed Moore’s law for the past decades, which predicts a doubling of the number of transistors that can be implemented on a chip every 18 months. However, tightly coupled with the evolution of the technology capabilities, the...
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| Format: | Others |
| Language: | English |
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KTH, Skolan för elektroteknik och datavetenskap (EECS)
2020
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| Online Access: | http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-280351 |