Analysis of Transient-Execution Attacks on the out-of-order CHERI-RISC-V Microprocessor Toooba
Transient-execution attacks have been deemed a large threat for microarchitectures through research in recent years. In this work, I reproduce and develop transient-execution attacks against RISC-V and CHERI-RISC-V microarchitectures. CHERI is an instruction set architecture (ISA) security extension...
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| Format: | Others |
| Language: | English |
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KTH, Skolan för elektroteknik och datavetenskap (EECS)
2021
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| Online Access: | http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-291743 |