Source and drain engineering in SiGe-based pMOS transistors

Source and drain engineering in SiGe-based pMOS transistors

A new shallow junction formation process, based on selective silicon etching followed by selective growth of in situ B-doped SiGe, is presented. The approach is advantageous compared to conventional ion implantation followed by thermal activation, because perfectly abrupt, low resistivity junctions...

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Bibliographic Details
Main Author: Isheden, Christian
Format: Doctoral Thesis
Language:English
Published: KTH, Mikroelektronik och Informationsteknik, IMIT 2005
Subjects:
Electronics
SiGe
source/drain
shallow junctions
pMOS
process integration
CVD
epitaxy
etching
Ni silicide
contact resistivity
Elektronik
Online Access:http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-96

Internet

http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-96

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