Design and Evaluation of A Low-Voltage, Process-Variation-Tolerant SRAM Cache in 90nm CMOS Technology

Design and Evaluation of A Low-Voltage, Process-Variation-Tolerant SRAM Cache in 90nm CMOS Technology

This thesis presents a novel six-transistor SRAM intended for advanced microprocessor cache application. The objectives are to reduce power consumption through scaling the supply voltage and to design a SRAM that is fully process-variation-tolerant, utilizing separate read and write access ports as...

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Bibliographic Details
Main Author: Fazli Yeknami, Ali
Format: Others
Language:English
Published: Linköpings universitet, Institutionen för systemteknik 2008
Subjects:
SRAM
traditional 6T
asymmetric 6T
memory
SNM
cell
Electronics
Elektronik
Online Access:http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-12260

Internet

http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-12260

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