Design of a Low Power, High Performance Track-and-Hold Circuit in a 0.18µm CMOS Technology

Design of a Low Power, High Performance Track-and-Hold Circuit in a 0.18µm CMOS Technology

This master thesis describes the design of a track-and-hold (T&H) circuit with 10bit resolution, 80MS/s and 30MHz bandwidth. It is designed in a 0.18µm CMOS process with a supply voltage of 1.8 Volt. The circuit is supposed to work together with a 10bit pipelined analog to digital converter....

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Bibliographic Details
Main Author: Säll, Erik
Format: Others
Language:English
Published: Linköpings universitet, Institutionen för systemteknik 2002
Subjects:
Electronics
track-and-hold
CMOS
0.18
low power
high performance
10-bit
folded cascode
switch theory
correlated double sampling
CDS
fully differential
gain boosting
regulated cascode
transmission gate
transmission gate switch
clock generator
clock driver
bias
bias circuit
amplifier design
switch design
common mode feedback
CMFB
80MSPS
80MS/s
Elektronik
Online Access:http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-1353

Internet

http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-1353

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