Implementation of a Program Address Generator in a DSP processor

Implementation of a Program Address Generator in a DSP processor

The purpose of this thesis is to construct a"Program Address Generator"(PAG) to a 24-bit Harvard type, RISC DSP processor using the VHDL language. The PAG is a part of the program control unit, and should consist of the following units: A system stack for storing jump and loop information...

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Bibliographic Details
Main Author: Waltersson, Roland
Format: Others
Language:English
Published: Linköpings universitet, Institutionen för systemteknik 2003
Subjects:
Electronics
DSP
Program Control Unit
VHDL
fetch
pipeline
branch hazard
RISC
stack
program counter
status register
Elektronik
Online Access:http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-1742

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http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-1742

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