Implementation of Pipelined Bit-parallel Adders
Bit-parallel addition can be performed using a number of adder structures with different area and latency. However, the power consumption of different adder structures is not well studied. Further, the effect of pipelining adders to increase the throughput is not well studied. In this thesis four di...
| Main Author: | |
|---|---|
| Format: | Others |
| Language: | English |
| Published: |
Linköpings universitet, Institutionen för systemteknik
2003
|
| Subjects: | |
| Online Access: | http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-1943 |