Design and Evaluation of High Density 5T SRAM Cache for Advanced Microprocessors
This thesis presents a five-transistor SRAM intended for the advanced microprocessor cache market. The goal is to reduce the area of the cache memory array while maintaining competitive performance. Various existing technologies are briefly discussed with their strengths and weaknesses. The design m...
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ndltd-UPSALLA1-oai-DiVA.org-liu-22862013-01-08T13:46:21ZDesign and Evaluation of High Density 5T SRAM Cache for Advanced MicroprocessorsengKonstruktion och utvärdering av kompakta 5T SRAM cache för avancerade mikroprocessorerCarlson, IngvarLinköpings universitet, Institutionen för systemteknikInstitutionen för systemteknik2004ElectronicsSRAMhigh-densitycachefive-transistor5TmemorymicroprocessorElektronikElectronicsElektronikThis thesis presents a five-transistor SRAM intended for the advanced microprocessor cache market. The goal is to reduce the area of the cache memory array while maintaining competitive performance. Various existing technologies are briefly discussed with their strengths and weaknesses. The design metrics for the five-transistor cell are discussed in detail and performance and stability are evaluated. Finally a comparison is done between a 128Kb memory of an existing six-transistor technology and the proposed technology. The comparisons include area, performance and stability of the memories. It is shown that the area of the memory array can be reduced by 23% while maintaining comparable performance. The new cell also has 43% lower total leakage current. As a trade-off for these advantages some of the stability margin is lost but the cell is still stable in all process corners. The performance and stability has been validated through post-layout simulations using Cadence Spectre. Student thesisinfo:eu-repo/semantics/bachelorThesistexthttp://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2286LiTH-ISY-Ex, ; 3481application/pdfinfo:eu-repo/semantics/openAccess |
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English |
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Others
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Electronics SRAM high-density cache five-transistor 5T memory microprocessor Elektronik Electronics Elektronik |
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Electronics SRAM high-density cache five-transistor 5T memory microprocessor Elektronik Electronics Elektronik Carlson, Ingvar Design and Evaluation of High Density 5T SRAM Cache for Advanced Microprocessors |
description |
This thesis presents a five-transistor SRAM intended for the advanced microprocessor cache market. The goal is to reduce the area of the cache memory array while maintaining competitive performance. Various existing technologies are briefly discussed with their strengths and weaknesses. The design metrics for the five-transistor cell are discussed in detail and performance and stability are evaluated. Finally a comparison is done between a 128Kb memory of an existing six-transistor technology and the proposed technology. The comparisons include area, performance and stability of the memories. It is shown that the area of the memory array can be reduced by 23% while maintaining comparable performance. The new cell also has 43% lower total leakage current. As a trade-off for these advantages some of the stability margin is lost but the cell is still stable in all process corners. The performance and stability has been validated through post-layout simulations using Cadence Spectre. |
author |
Carlson, Ingvar |
author_facet |
Carlson, Ingvar |
author_sort |
Carlson, Ingvar |
title |
Design and Evaluation of High Density 5T SRAM Cache for Advanced Microprocessors |
title_short |
Design and Evaluation of High Density 5T SRAM Cache for Advanced Microprocessors |
title_full |
Design and Evaluation of High Density 5T SRAM Cache for Advanced Microprocessors |
title_fullStr |
Design and Evaluation of High Density 5T SRAM Cache for Advanced Microprocessors |
title_full_unstemmed |
Design and Evaluation of High Density 5T SRAM Cache for Advanced Microprocessors |
title_sort |
design and evaluation of high density 5t sram cache for advanced microprocessors |
publisher |
Linköpings universitet, Institutionen för systemteknik |
publishDate |
2004 |
url |
http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2286 |
work_keys_str_mv |
AT carlsoningvar designandevaluationofhighdensity5tsramcacheforadvancedmicroprocessors AT carlsoningvar konstruktionochutvarderingavkompakta5tsramcacheforavancerademikroprocessorer |
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1716528656165109760 |