Power Estimation of High Speed Bit-Parallel Adders
Fast addition is essential in many DSP algorithms. Various structures have been introduced to speed up the time critical carry propagation. For high throughput applications, however, it may be necessary to introduce pipelining. In this report the power consumption of four different adder structures,...
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| Format: | Others |
| Language: | English |
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Linköpings universitet, Institutionen för systemteknik
2004
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| Online Access: | http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2390 |