Parallel JPEG Processing with a Hardware Accelerated DSP Processor

Parallel JPEG Processing with a Hardware Accelerated DSP Processor

This thesis describes the design of fast JPEG processing accelerators for a DSP processor. Certain computation tasks are moved from the DSP processor to hardware accelerators. The accelerators are slave co processing machines and are controlled via a new instruction set. The clock cycle and power c...

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Bibliographic Details
Main Authors: Andersson, Mikael, Karlström, Per
Format: Others
Language:English
Published: Linköpings universitet, Institutionen för systemteknik 2004
Subjects:
Datorteknik
JPEG
JFIF
2-D DCT
Huffman
Accelerator
HW/SW partitioning
Computer Engineering
Online Access:http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2615

Internet

http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2615

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