Improved implementation of a 1K FFT with low power consumption
In this master thesis, a behavioral VHDL model of a 1k Fast Fourier Transform (FFT) algorithm has been improved, first to make it synthesizable and second to obtain a low power consumption. The purpose of the thesis has not been to focus on the FFT algorithm itself or the theory behind it. Instead t...
| Main Authors: | , |
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| Format: | Others |
| Language: | English |
| Published: |
Linköpings universitet, Institutionen för systemteknik
2005
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| Online Access: | http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2881 |