Implementation of a Zero Aware SRAM Cell for a Low Power RAM Generator
In this work, an existing generator for layout of Static Random Access Memory (SRAM) is improved. The tool is completed with a block decoder, which was missing when the thesis started. A feature of generating schematic files is also added. The schematics are important to get a better overview, to te...
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| Format: | Others |
| Language: | English |
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Linköpings universitet, Institutionen för systemteknik
2005
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| Online Access: | http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-371 |