Integrated Optimal Code Generation for Digital Signal Processors

Integrated Optimal Code Generation for Digital Signal Processors

In this thesis we address the problem of optimal code generation for irregular architectures such as Digital Signal Processors (DSPs). Code generation consists mainly of three interrelated optimization tasks: instruction selection (with resource allocation), instruction scheduling and register alloc...

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Bibliographic Details
Main Author: Bednarski, Andrzej
Format: Doctoral Thesis
Language:English
Published: Linköpings universitet, PELAB 2006
Subjects:
Instruction-level parallelism
integrated code generation
dynamic programming
instruction scheduling
instruction selection
clustered VLIW architecture
integer linear programming
architecture description language
Computer science
Datavetenskap
Online Access:http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-6568
http://nbn-resolving.de/urn:isbn:91-85523-69-0

Internet

http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-6568
http://nbn-resolving.de/urn:isbn:91-85523-69-0

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