Verifieringsplattform i SystemVerilog
Our task was to create a virtual test bench for verifying memory addresses in our commissioning body’s models. The purpose with the testbench was that it should be created in such a way that it would be easy to change the device under test without any major changes in the testbench. To solve the pro...
| Main Authors: | , |
|---|---|
| Format: | Others |
| Language: | Swedish |
| Published: |
Linköpings universitet, Elektroniksystem
2011
|
| Subjects: | |
| Online Access: | http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-71606 |