Interfacing a processor core in FPGA to an audio system
The thesis project consists on developing an interface for a Nios II processor integrated in a board of Altera (UP3- 2C35F672C6 Cyclone II). The main goal is show how the Nios II processor can interact with the other components of the board.The Quartus II software has been used to create to vhdl cod...
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| Format: | Others |
| Language: | English |
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Linköpings universitet, Institutionen för systemteknik
2006
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| Online Access: | http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-7191 |