Hardware Accelerator for Duo-binary CTC decoding : Algorithm Selection, HW/SW Partitioning and FPGA Implementation
Wireless communication is always struggling with errors in the transmission. The digital data received from the radio channel is often erroneous due to thermal noise and fading. The error rate can be lowered by using higher transmission power or by using an effective error correcting code. Power con...
| Main Authors: | , |
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| Format: | Others |
| Language: | English |
| Published: |
Linköpings universitet, Institutionen för systemteknik
2006
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| Online Access: | http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-7902 |