FPGA Implementation of Flexible Interpolators and Decimators
The aim of this thesis is to implement flexible interpolators and decimators onField Programmable Gate Array (FPGA). Interpolators and decimators of differentwordlengths (WL) are implemented in VHDL. The Farrow structure is usedfor the realization of the polyphase components of the interpolation/dec...
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| Format: | Others |
| Language: | English |
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Linköpings universitet, Elektroniksystem
2013
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| Online Access: | http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-89761 |