Hardware implementation of a Partial Dynamic Reconfiguration Controller
Partial Dynamic Reconfiguration (PDR) of Field Programmable Gate Arrays (FPGAs) wasintroduced to overcome the need for more resources on the FPGA fabric. This enabled parts of thedevice to be reconfigured at runtime, while the rest of the system continued to function without anyinterruptions. Theref...
| Main Author: | |
|---|---|
| Format: | Others |
| Language: | English |
| Published: |
Linköpings universitet, Institutionen för datavetenskap
2013
|
| Online Access: | http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-94686 |