Hardware Accelerator of Matrix Multiplication on FPGAs : Hardware Accelerator of Matrix Multiplication on FPGAs
To solve the computational complexity and time-consuming problem of large matrix multiplication, this thesis design a hardware accelerator using parallel computation structure based on FPGA. After function simulation in ModelSim, matrix multiplication functional modules as a custom component used as...
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| Format: | Others |
| Language: | English |
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Uppsala universitet, Institutionen för informationsteknologi
2018
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| Online Access: | http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-366815 |